A common requirement in integrated circuit fabrication is the etching of openings such as contacts, vias and trenches in dielectric materials. The dielectric materials include doped silicon oxide such as fluorinated silicon oxide (FSG), undoped silicon oxide such as silicon dioxide, silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, organosilicate glass, etc. The dielectric dopants include boron, phosphorus and/or arsenic. The dielectric can overlie a conductive or semiconductive layer such as polycrystalline silicon, metals such as aluminum, copper, titanium, tungsten, molybdenum or alloys thereof, nitrides such as titanium nitride, metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, molydenum silicide, etc.
Various plasma etching techniques for etching openings in silicon oxide are disclosed in U.S. Pat. Nos. 5,013,398; 5,013,400; 5,021,121; 5,022,958; 5,269,879; 5,529,657; 5,595,627; 5,611,888; and 5,780,338. The plasma etching can be carried out in medium density reactors such as the parallel plate plasma reactor chambers described in the '398 patent or the triode type reactors described in the '400 patent or in high density reactors such as the inductive coupled reactors described in the '657 patent. Etching gas chemistries include the oxygen-free, Ar, CHF3 and optional CF4 gas mixture described in the '121 and '958 patents, the oxygen-free, fluorine-containing and nitrogen gas mixture described in the '879 patent, the C4F8 and CO gas mixture described in the '627 patent, the oxygen and CF4 gas mixture described in the '400 patent, the oxygen, CF4 and CH4 gas mixture described in the '657 patent, and the Freon and neon gas mixture described in the '888 patent.
U.S. Pat. No. 5,736,457 describes single and dual “damascene” metallization processes. In the “single damascene” approach, vias and conductors are formed in separate steps wherein a metallization pattern for either conductors or vias is etched into a dielectric layer, a metal layer is filled into the etched grooves or via holes in the dielectric layer, and the excess metal is removed by chemical mechanical planarization (CMP) or by an etch back process. In the “dual damascene” approach, the metallization patterns for the vias and conductors are etched in a dielectric layer and the etched grooves and via openings are filled with metal in a single metal filling and excess metal removal process.
U.S. Pat. No. 6,153,514 discloses a method of forming a self-aligned dual damascene structure which includes a lower conductive layer (e.g., copper or copper alloy), a first etch stop layer (e.g., silicon nitride), a first dielectric layer (e.g., low k dielectric material wherein k<4), a second etch stop layer (e.g., silicon nitride), a second dielectric layer (e.g., low k dielectric material), a hard mask layer (e.g., silicon nitride), and a photoresist layer patterned to provide the feature to be etched into the second dielectric layer. According to this patent, the nitride hard mask layer is etched with CHF3/N2, the second dielectric layer is etched with N2/H2O2 or N2/H2, the second etch stop layer is etched with CHF3/N2 and the first dielectric layer is etched with C4F8/Ar/O2/CO.
U.S. Pat. No. 6,156,642 discloses a dual damascene structure wherein a semiconductor substrate includes a bottom metallization layer (e.g., copper), a topping layer (e.g., silicon nitride), a dielectric layer (e.g., silicon oxide or other low k material), a conformal layer (e.g., titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride) covering sidewalls of a trench and via hole, and a passivation layer (e.g., silicon nitride or silicon carbide). U.S. Pat. No. 6,143,641 discloses a dual damascene structure in an integrated circuit structure which includes an intermetal dielectric material (e.g., SiO2) on an underlying conductive material (e.g., aluminum or copper), an adhesion layer (e.g., Ti, TiN, Ta) on exposed sidewalls of the dual damascene via structure which is filled with copper, a barrier metal or layer of silicon nitride, and additional layers including a low k dielectric material, silicon dioxide and silicon nitride.
U.S. Pat. No. 6,168,726 discloses a method of etching oxidized organo-silane films containing hydrogen, carbon, silicon and oxygen. This patent describes a carbon-based low-k material identified as byvinylsiloxane-benzocyclobutene (BCB) which contains a few percent of silicon but is otherwise an organic polymer containing carbon, oxygen and hydrogen. Another material disclosed in this patent is identified as Black Diamond marketed by Applied Materials, Inc., the film being an oxidized organo-silane film having, in atomic percent, 40-52% H, 5-11% C, 18-23% Si and 21-37% oxygen.
U.S. Pat. No. 6,153,935 discloses a damascene structure which includes a dielectric layer of silicon dioxide, polyimide, an organic siloxane polymer, poly-arylene ether, carbon-doped silicate glass or silsesquioxane glass, spin-on glass, fluorinated or non-fluorinated silicate glass, diamond-like amorphous carbon or other low dielectric constant material and a CMP stop layer in the form of a thin (about 20 to about 100 nm thick) layer of a dielectric silicon-based compound of low dielectric constant such as silicon nitride or silicon carbide, or a silicon-containing material of lower dielectric constants such as hydrogenated silicon carbide, silicon oxynitride or non-silicon-containing polymer such as one derived from benzocyclobutene.
U.S. Pat. No. 6,147,021 discloses a process for forming low dielectric constant (low-k) dielectric material wherein low-k materials are defined as those having a dielectric constant of 3.0 or less. U.S. Pat. No. 6,054,379 discloses a process of depositing a low-k dielectric layer on a patterned metal layer by reaction of an organosilane compound and an oxidizing compound.
U.S. Pat. No. 6,090,304 discloses a method of plasma etching semiconductor substrates in a dual frequency plasma reactor wherein a first radiofrequency (RF) source is coupled to a top showerhead electrode through an RF matching network and a bottom electrode (on which a semiconductor wafer is supported) is coupled to a second RF source through a second matching network.
As device geometries become smaller and smaller, the need for high etch selectivity ratios is even greater in order to achieve plasma etching of deep and narrow openings in dielectric layers such as low-k materials. Accordingly, there is a need in the art for a plasma etching technique which provides high etch selectivity ratios with respect to an overlying mask layer and/or which achieves deep and narrow openings.